Advanced VLSI DESIGN

At the completion of the program the learners will be able to:

• Discuss the concepts of Analog and Digital circuit design, advanced semiconductor technologies such as FinFET, CFET , GAA , and SOI and Scripting Languages such as Python and TCL
• Analyse the core principles of CMOS and emerging device architectures, along with advanced circuit theory and layout fundamentals
• Apply the concept of FinFET to design and simulate complex full-custom layout design blocks such as op-amps, LDOs, LNAs, PLLs, data converters, and bandgap references using industry-standard PDKs and EDA tools
• Analyse and interpret circuit schematics and translate them into matched, optimized, and DRC/LVS-compliant layouts
• Analyse and apply layout-dependent effects, parasitic effects, and process variations and evaluate strategies for performance, noise immunity, and device matching using layout-aware techniques
• Analyze post-layout simulation results and iterate to meet performance specifications under PVT variations
• Design and implement optimized Analog and Digital IPs, perform pre- and post-layout simulations, and validate manufacturability and robustness using DRC, LVS, DFM, and reliability checks

At the completion of the program the learners will be able to:

• Discuss the foundational concepts in digital design and scripting languages like TCL, Python, Linux, Verilog, SystemVerilog, UVM constrained randomization, functional coverage, assertions, DPI, and formal verification
• Develop synthesizable RTL designs and construct reusable and scalable UVM-based testbenches to verify design correctness and corner cases
• Apply verification methodologies including constrained random testing, coverage analysis, and assertion-based verification
• Identify and resolve functional issues using simulation and debugging tools
• Analyze formal verification methods to ensure implementation readiness
• Apply synthesis-driven design principles, verification of IPs and SoC-level components using AMBA protocols, and coverage analysis to ensure functional correctness

At the completion of the program the learners will be able to:

• Discuss the core concepts of physical design principles, device physics, CMOS and advanced CMOS technologies including FinFET, GAA, SOI and scripting languages like Python and TCL
• Apply core concepts of digital logic, synthesis, timing and power analysis to design, implement, and validate full-custom and semi-custom digital ICs using industry-standard EDA tools
• Implement Design for Test concepts, including scan chain insertion, ATPG , and BIST in scenarios mimicking realistic tapeout processes
• Develop complete physical design flows, including floorplanning, Placement and Routing , Clock Tree Synthesis , power, Performance and area, Engineering Change Orders , and signoff methodologies
• Implement the complete ASIC physical design flow from netlist to GDSII using industry tools e.g., Cadence Innovus, Synopsys , including physical verification steps like DRC, LVS, ERC, and Antenna Checks, and resolving associated violations
• Perform Static Timing Analysis and power-aware validation while addressing critical design metrics such as IR drop, crosstalk, routing congestion, signal integrity, and parasitics
• Analyze post-layout simulation results under PVT variations, iterate to meet performance targets, and apply mitigation techniques for challenges in advanced technology nodes

At the completion of the program the learners will be able to:

• Apply the ASIC design flow by prototyping RTL designs on FPGA using Verilog HDL. Demonstrate the ability to translate design specifications into synthesizable hardware, progressing through design entry, functional simulation, and hardware validation stages
• Utilize EDA tools to perform synthesis, simulation, and static timing analysis. Analyze timing reports and simulation results to validate functionality and timing closure, while ensuring design quality through Lint, Clock Domain Crossing, and Reset Domain Crossing checks
• Construct and integrate FSMs, subsystems, and IP blocks into larger digital systems. Interface and validate communication with peripherals using UART, SPI, I2C protocols, and analyze the integration of bus protocols like AXI, AHB, and APB for efficient data transfer
• Implement basic RISC-V based designs on FPGA and analyze system behavior through testbenches and debugging techniques. Develop automation scripts using Linux shell and TCL, while enhancing employability through structured resume building and mock interview practice

At the completion of the program, learners will be able to:

• Design and implement combinational and sequential digital circuits using Verilog HDL, adhering to RTL coding guidelines.
• Write synthesizable Verilog code for core digital components including FSMs, counters, and memory elements.
• Program and verify FPGA-based implementations to validate digital designs practically.
• Design and integrate UART, I2C, and SPI communication protocols using FPGA platforms.
• Apply debugging and simulation techniques to identify and fix functional issues in digital systems.

At the completion of the program, learners will be able to:

• Develop synthesizable RTL code using Verilog HDL, applying correct modelling styles, sensitivity handling, and timing constructs.
• Apply System Verilog features such as arrays, queues, classes, and OOP concepts to construct scalable and reusable testbenches.
• Use assertions, constraints, and randomization techniques to perform functional verification.
• Simulate, debug, and verify digital designs using EDA tools and analyze behavior through waveform.